module edge_check (
	input wire clk,    // Clock
	input wire rst,
	input wire singal ,
	output logic posedge_checked ,
	output logic negedge_checked 
	
);
	logic temp ;
	always_ff @(posedge clk) begin
		if(rst)begin
			temp <= 0 ;
		end else begin
			temp <= singal ;
		end
	end


	assign negedge_checked = temp & ~singal ;//negedge 

	assign posedge_checked = ~temp & singal ;


	

endmodule : edge_check